This invention relates to a circuit and a method for timing multi-level non-volatile memories.
In particular, the invention relates to a read timing circuit for regulating the step of reading from a multi-level non-volatile memory, which circuit is adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path, which dummy path includes at least one dummy wordline being applied a supply voltage and associated with a dummy decoding circuit portion arranged to receive an ATD signal.
As is well known, in a two-level non-volatile memory which employs a floating-gate NMOS transistor as an elementary cell, a capability to modulate the threshold voltage of the memory cell is utilized for discriminating between two logic states. A first logic state (logic xe2x80x9c1xe2x80x9d) corresponds to a situation of no charge being contained in the floating gate, as would be typical of a virgin or an erased cell. The other logic state (logic xe2x80x9c0xe2x80x9d) corresponds to the floating gate having a sufficient number of electrons stored therein to produce a substantial rise of its threshold, signifying a programmed state of the cell.
To read from the memory cell, the gate is applied a read voltage Vread, and the current flowing through the cell is sensed: if the cell is written, its threshold voltage is higher than Vread and, therefore, no current will be passed. On the other hand, if the cell has been erased, its threshold voltage must be adequate to let current flow through it. The threshold voltage spread of the cells, following an electric erasement, is in the range of about 1V to 2.5V. Ensuring that there are no depleted cells and avoiding damage to the thin oxide of the transistor which comprises the cell, during the reading operation, are the governing factors for the lower limit, the upper limit being instead dictated by the intrinsic extent of the spread. The programmed spread would generally lie above 5V.
But in the instance of multi-level non-volatile memories, this spread is entirely different. In these memory types, the charge stored on the floating gate is further split into a number of spreads equal to 2n, where xe2x80x9cnxe2x80x9d is the number of bits to be stored in the same cell. Thus, with two bits per cell, there would be four spreads.
Comparative threshold voltage spreads, for a two-level memory and a multi-level memory having two bits per cell, are illustrated schematically by the plots in FIGS. 1A and 1B. As can be seen, the multi-level structure involves a reduction in the gap between voltage values, and an increased read voltage.
Also known is that memory cells are organized as rows and columns of a matrix, and that the physical organization of the memory matrix is decided by two fundamental considerations:
space occupation to be the least possible, for obvious reasons of cost; and
memory access time, that is the time taken by the device to present the contents of the addressed location on its outputs, to fill ever stricter user""s specifications. (Some 100 ns, nowadays.)
With access time being fundamental in determining the quality of a memory, this parameter is foremost in the designer""s choices, above all of the matrix row size.
Schematized in FIG. 2 is the structure of a non-volatile memory of the NOR type. The gate terminals of the cells are interconnected at the rows or wordlines of the matrix, and the drain terminals are connected together to provide the columns or bitlines of the matrix.
Row and column binary decoders are respectively associated with the rows and the columns of the matrix, and enable each cell to be located univocally by addresses provided from outside the memory. The source terminals of the cells are connected to a common xe2x80x9csource line,xe2x80x9d which is the same as a voltage reference, e.g., a ground reference, in the instance of EPROMs.
In Flash EEPROMs which allow for the memory matrix to be erased electrically, the source line is instead driven by purposely arranged circuitry.
The drain terminals are usually connected to form the bitlines by a metallization line. The gate terminals of one row are interconnected by a strip of a conductive material such as polysilicon (polycrystalline silicon). This strip of polysilicon, additionally to interconnecting the gates, is used to form the control gates of the memory cells.
FIG. 3 is an enlarged scale, schematic vertical cross-section view of a portion of a memory matrix, specifically a cell pair in a row. The cross-section in which the cell pair appear is taken at half-length of the polysilicon strip.
FIG. 3A shows schematically the electric equivalent of FIG. 3.
The polysilicon layer (Poly 2) which comprises and connects the control gates is doped quite different from the underlying layer of polysilicon (Poly 1) which provides the floating gate. By regarding the capacitive couplings between these conductive layers of Poly1 and Poly2 to be representative of capacitors with parallel planar plates separated by a dielectric layer of interpoly (FIG. 3B), the parasitic capacitance that associates with each cell can be readily calculated at values lying typically somewhere between 0.2 and 0.4 fF per cell.
Resistivity per square of the layer Poly2 is usually some ten Ohms. With the cell size and technological parameters being known factors, the time delay associated with the voltage rise across the wordline can now be calculated.
As an introductory approximation, a concentrated parameter model can be taken into consideration, with the time constant xcfx84 associated with the row given as:
xcfx84row=Rcell*Ccell*Ncellxe2x80x83xe2x80x83(1)
Assuming the row rise time to amount to no more than 10% of the overall access time, the maximum number of cells that can be connected to the same row can be calculated. The row time constant would usually be some ten nanoseconds.
The wordline voltage is therefore described by the following law:
Vrow=Vread*(1xe2x88x92exe2x88x92t/xcfx84row)xe2x80x83xe2x80x83(2)
The problems connected with the operation of reading the contents of the memory cells will now be reviewed.
Shown in FIG. 4 is a diagram of a conventional sense amplifier. The current flowed through a matrix cell and that through a reference cell are routed to a current/voltage I/V converter having outputs MAT and REF which represent the inputs to a final comparator operative to present the data in digital form.
The diode connection of P-channel transistors M12 and M13 in the I/V converter may be provided in either the matrix leg or the reference leg, as required. Gates NOR1 and NOR2 function, in combination with transistors M14 and M15, to prevent xe2x80x9csoft-writingxe2x80x9d or spurious cell writing during a reading operation. These elements form a feed-back cascode type of arrangement which restrains the drain terminal of the cell from exceeding a potential of 1V. Transistors M6, M7 and M8 are used for column decoding in the matrix. The basic layout just described is added auxiliary circuitry for improved dynamic performance, i.e., reading speed, of the sense amplifier.
A primary task of the auxiliary circuitry is to equalize, i.e., short-circuit, the critical nodes of the converter, biasing them to an optimum value from the standpoint of switch-over speed.
FIG. 5 shows an example of equalizing circuitry. This circuitry is only active as a signal SAEQ is at a logic high, and does not alter the sense amplifier operation when the signal is in the other of its states. Transistor M1 is operative to short-circuit the nodes MAT and REF directly. To obtain a perfectly even starting situation, the cascodes and drain nodes of the column decoders are usually equalized. Transistors M1 and M2 are low-threshold native transistors, while transistor M3 is a thick-oxide transistor because the bitline node is applied a relatively high (4 to 5V) programming voltage Vp.
The equalizing step allows the nodes to be reset at each reading, bringing them to a convenient voltage value. Transistors M4 and M5 are to provide increased current during the equalizing step for charging the bitline parasitic capacitances. Finally, the P-channel transistors which separate M4 and M5 from the supply serve a protective function against electrostatic discharges.
In essence, the equalizing step allows the voltage variation at the nodes MAT and REF to be minimized, as well as ensuring the same bias at each reading. In fact, the nodes are reset always to the same potential, irrespective of what may have occurred during the previous reading.
FIG. 6 shows a comparative graph vs. the same time base of the signals which appear in the sense amplifier during the equalizing step.
Generating and controlling the equalization signal SAEQ frequently poses hard problems to solve.
A first requirement is that the signal SAEQ should be related to the start of each new reading directly. Every memory of the asynchronous type includes circuitry operative to sense any changes occurring at address terminals outside the memory matrix which are connected to the decoders. This circuitry is to generate a suitable ATD (Address Transition Detection) pulsive signal. FIG. 7 illustrates schematically a correlation of the address transition occurring at the memory input terminal and the generation of the ATD pulse. Each new ATD pulse indicates a need for a new equalization pulse SAEQ.
The following considerations dictate the duration of the pulse SAEQ:
1) for maximum effectiveness of the equalizing step, this step should end while the addressed cell is still pulling its respective current; in other words, the comparator should commit to the correct side immediately;
2) the duration of the equalizing step should not be drawn out beyond necessity, so as not to incur a time penalty which would nullify all advantage; and
3) the converter nodes should be given time to attain start-up voltage.
It can be appreciated from the above considerations that the lower limit for the signal SAEQ is set by the time required to correctly bias the cell, both as regards gate voltage and drain voltage. In fact, the floating gate transistor would be a MOS transistor in all cases, and its drain current would be dependent on both gate voltage and drain voltage, given that the source terminal is at ground potential.
As said before, the wordline charge lies close to an RC charge having a 10 ns value. Biasing the drain terminal usually takes less time than the wordline, because it is achieved through a metallization connection and, therefore, uninfluenced by the RC effects typical of polysilicon conductors.
The problems posed by generating the equalizing pulse have been addressed in the state of the art, and a number of solutions offered.
Only the closing phase of the pulse SAEQ will be considered herein below, as the start-up phase is dependent on the ATD signal.
The simplest solution is that of providing a delay chain to set the duration of the signal SAEQ based on the ATD signal. Once the wordline time constant is calculated, the performance of the sense amplifier can be assessed by computer simulation, and an optimum value for the signal SAEQ be found. However, this solution has a serious drawback in that it cannot follow variations in the technological process of fabricating the electronic storage device (the so-called xe2x80x9cprocess spreadxe2x80x9d) automatically.
The delay brought about by the wordline charging is related directly to the resistivity of the strip of Poly2. Since forming a polysilicon layer with resistivity of a few Ohms is one of the most critical processing steps, the spread of this parameter can be substantial.
The solution provided by the use of a delay chain is, therefore, rather inflexible, in the sense that hardware provisions, such as one or more masks for application during the process of fabricating the memory circuit, become necessary to vary it.
A more flexible solution than this consists of using a xe2x80x9cdummyxe2x80x9d row as shown schematically in FIG. 8. A dummy row is identical with (i.e., has the same time constant as) a matrix row, but locates outside the addressing space. Each time that a new ATD pulse occurs, the decoding portion and dummy wordlines are activated concurrently. The dummy row is connected to a comparator which will determine the moment that the dummy row attains a given percent of the supply voltage Vdd. In general, the signal SAEQ can be constructed here using a set/reset type of flip-flop. The ATD pulsive signal will act on the set terminal, while the comparator output will cause the signal SAEQ to be reset.
Should the wordline time constant be increased by variations in the technological parameters, the above circuit is capable of retarding the signal SAEQ as appropriate.
While being in many ways advantageous, this solution is unsuitable for application to multi-level storage devices.
Assume the power supply to be at 5V. As shown in FIG. 1, the supply voltage Vdd is adequate for reading two-level cells, but not multi-level cells which would require at least 6V in view of the current allowances demanded by the sense amplifier for discriminating between currents at either voltage levels.
Thus, multi-level cells need timing circuitry which would indicate the moment the row attains a read voltage Vread of at least 6V, although receiving a lower supply voltage. In this context, moreover, the wordline voltage should be determined with great accuracy, due to multi-level reading being allowed typically narrow margins.
A current market trend for non-volatile memories favors memories having a single power supply, to meet the requirements of portable applications, such as cellular telephones, palm-tops, etc. With a single power supply, all voltages above the supply voltage Vdd must be generated internally by means of voltage boosters.
A major problem with the use of voltage boosters is their limited current capacity, hardly higher than one mA. Where stable voltages are demanded, it is further necessary to provide a suitable regulator, interposed between the voltage booster and the utility, and the regulator effectiveness clearly is also tied to the dynamic current draw that occurs during row decode switch-overs. In other words, the utilization of the read voltage Vread should be restrained as far as possible in order to retain its stability. In the light of such considerations, it can be appreciated that the simplest solution available for two-level memories, i.e., that of supplying the same read voltage to both the dummy comparator and its reference, is useless with multi-level structures.
An embodiment of this invention provides a timing circuit for a multi-level non-volatile memory with appropriate structural and functional features to allow the duration of the equalization signal needed for a memory reading operation to be regulated in a fully independent manner of the fabricating process spread, thereby to overcome the limitations of prior art solutions.
A principle on which this invention stands proceeds from the observation that the wordline transient is independent of the absolute value of the voltage that it should attain, and is only dependent on the time constant associated therewith. In other words, the wait time for a given percent of the read voltage to be attained is not tied to this voltage value.
An embodiment of the invention is directed to a read timing circuit for regulating reading from a multi-level non-volatile memory by generating and issuing an equalization signal to a sense amplifier placed downstream of a dummy path. The dummy path includes a dummy wordline to which is applied a supply voltage and is associated with a dummy decoding circuit portion arranged to receive an ATD signal. The read timing circuit includes a differential cell comparator having a first input connected downstream of the dummy path, a second input arranged to receive a reference signal, and an output at which an electric signal is generated upon said dummy wordline attaining a potential that is a predetermined percentage of said supply voltage.